<div class="content-intro"><p style="text-align: left;"><span style="font-size: 12pt;">SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value.</span></p></div><h3><strong>About the team</strong></h3> <p>The Design Verification team works on the RDU, SambaNova's chip for machine learning and AI workloads. This group focuses on chip-level control and initialization: sequencing, state transitions, clocking, and recovery across multiple subsystems on the chip. You'll build SystemVerilog and UVM verification environments alongside architects, RTL designers, and firmware engineers, and take ownership of verification plans from first draft through closure. The team works closely with the broader verification organization, so debugging and root-causing issues often means coordinating across groups rather than working in isolation.</p> <h3><strong>About the role</strong></h3> <p>SambaNova Systems is looking for a talented and motivated Design Verification Engineer, DFT to help us build state of the art RDU chips for machine learning and artificial intelligence.</p> <h3><strong>Responsibilities</strong></h3> <ul> <li class="font-claude-response-body whitespace-normal break-words pl-2">Develop and execute comprehensive verification plans for complex chip-level control and initialization features</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Develop SystemVerilog/UVM based verification environments, test sequences, checkers, assertions, and functional coverage</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Verify complex sequencing, dependencies, state transitions, and recovery scenarios across multiple chip subsystems</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Develop directed and constrained-random tests to identify architectural and implementation corner cases</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Closely work with architects, RTL designers, firmware, and other verification teams to understand design intent and drive verification closure</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Debug simulation and regression failures and work with design teams to root-cause and resolve issues</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Analyze regression failures, functional and code coverage and drive verification to closure</li> </ul> <h3><strong>Required Qualifications</strong></h3> <ul class="[li_&]:mb-0 [li_&]:mt-1 [li_&]:gap-1 [&:not(:last-child)_ul]:pb-1 [&:not(:last-child)_ol]:pb-1 list-disc flex flex-col gap-1 pl-8 mb-3 print:block print:space-y-1"> <li class="font-claude-response-body whitespace-normal break-words pl-2">B.S. in Computer Science, Computer Engineering, or related field</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">5+ years relevant industry experience</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Strong understanding of digital design, SoC architecture, and verification methodologies</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Strong proficiency in SystemVerilog and UVM is required</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Experience with constrained-random verification, functional coverage, and assertion-based verification</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Good understanding of chip initialization, control sequencing, clocking, and cross-domain interactions</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Strong simulation debug and problem-solving skills</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Proficiency in scripting languages, e.g. Python, Perl, TCL and shell scripting, etc. is required</li> </ul> <h3><strong>Preferred Qualifications</strong></h3> <ul class="[li_&]:mb-0 [li_&]:mt-1 [li_&]:gap-1 [&:not(:last-child)_ul]:pb-1 [&:not(:last-child)_ol]:pb-1 list-disc flex flex-col gap-1 pl-8 mb-3 print:block print:space-y-1"> <li class="font-claude-response-body whitespace-normal break-words pl-2">Familiarity with CDC/RDC concepts and verification methodologies</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Fluency in Claude / AI tools for verification development and debug</li> </ul> <h3> </h3><div class="content-pay-transparency"><div class="pay-input"><div class="description"><p>Base Salary Range:</p></div><div class="title">Base Pay Range</div><div class="pay-range"><span>$120,000</span><span class="divider">—</span><span>$200,000 USD</span></div></div></div><div class="content-conclusion"><p><strong><span style="font-family: helvetica, arial, sans-serif; font-size: 12pt;">Submission Guidelines<br></span></strong><span style="font-family: helvetica, arial, sans-serif; font-size: 12pt;">Please note that in order to be considered an applicant for any position at SambaNova Systems, you must submit an application form for each position for which you believe you are qualified. </span></p> <p><strong><span style="font-family: helvetica, arial, sans-serif; font-size: 12pt;">EEO Policy<br></span></strong><span style="font-family: helvetica, arial, sans-serif; font-size: 12pt;">SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws.</span></p> <p style="text-align: left;"><span style="font-family: helvetica, arial, sans-serif; font-size: 12pt;"><strong>Benefits Summary for US-Based, Full-Time Employment Positions</strong><br>SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well-being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.</span></p></div>