<div class="content-intro"><p style="text-align: left;"><span style="font-size: 12pt;">SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. At the core of SambaNova's technology is the RDU (Reconfigurable Dataflow Unit) — a chip built on a dataflow architecture rather than the traditional GPU model. Its decode performance is especially strong for agentic workloads like multi-turn agents, code generation, and long-running applications. RDUs are packaged into SambaRack, rack-scale hardware that lets customers deploy state-of-the-art models with better performance, greater energy efficiency, and faster time to value.</span></p></div><h3><strong>About the team</strong></h3> <p>SambaNova's RDU is the processor behind our inference systems, and design verification ensures quality and reliability before production. The team owns verification for block, full-chip, and gate-level benches, performance verification, coverage closure, and the emulation and FPGA prototypes.</p> <h3><strong>About the role</strong></h3> <p class="font-claude-response-body break-words whitespace-normal">SambaNova is looking for a Principal Design Verification Engineer to own verification for our next-generation RDU, the reconfigurable dataflow silicon behind our machine learning and AI systems. This is a senior individual-contributor role where you'll own the test plan, testbench architecture, coverage model, and sign-off criteria, while shaping the team-wide infrastructure, reuse patterns, and verification practices.</p> <div data-testid="transcript-trailing"> <div class="flow-root"> <div> <div class="ml-[calc(var(--msg-text-inset,0.5rem)_-_0.25rem)] mt-6 flex items-center transition-transform duration-300 ease-out"> <div class="p-1 -translate-x-px" data-testid="chat-footer-spark"><span id="_r_bj_" class="inline-flex" data-base-ui-tooltip-trigger=""></span></div> </div> </div> </div> </div> <p class="font-claude-response-body break-words whitespace-normal">You'll work alongside principal engineers from the design, architecture, compiler, and runtime teams who have built and evolved this verification environment across several generations of silicon, to verify the chip against production ML workloads.</p> <h3><strong>Responsibilities</strong></h3> <p>Some of your responsibilities will include...</p> <ul> <li class="font-claude-response-body whitespace-normal break-words pl-2">Own verification end to end for a major subsystem of the RDU: test plan, testbench architecture, coverage model, and sign-off criteria</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Build the coverage model for your area, set the closure bar, and drive it to closure ahead of tape-out</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Develop testbench components, agents, checkers, and stimulus at block, full-chip, system, and gate level</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Serve as the technical authority for verification of your subsystem: review and arbitrate testbench design decisions, and lead debug on the hardest failures</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Own regression health and failure triage for your area: drive root cause, not just reproduction</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Verify functional and performance behavior</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Advance DV methodology beyond your own area: reusable infrastructure, verification IP integration, and AI-assisted verification workflows the rest of the team adopts</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Contribute to emulation and FPGA prototyping, and support silicon bring-up and post-silicon debug in the lab</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Set the technical bar through design and DV reviews, and mentor engineers to raise the level of the team's verification practice</li> </ul> <h3><strong>Required qualifications</strong></h3> <ul> <li class="font-claude-response-body whitespace-normal break-words pl-2">BS or MS in EE, CS, or CE with 7+ years (or equivalent) of industry experience in ASIC design verification</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Deep hands-on expertise in SystemVerilog and SVA with a standard methodology (UVM, OVM, or VMM), plus scripting in Python and C/C++</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Full-cycle DV ownership from test plan through tape-out on at least one complex ASIC or major subsystem, including owning a coverage model to closure</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Experience verifying digital logic in a CPU, GPU, SoC, or comparably complex ASIC</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Track record of debugging hard, intermittent, or low-reproducibility pre-silicon failures to root cause</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Demonstrated technical leadership without formal authority: setting direction in reviews, arbitrating testbench decisions, and mentoring engineers</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Working knowledge of modern computer architecture and of machine learning accelerators or SoCs</li> </ul> <h3><strong>Preferred qualifications</strong></h3> <ul> <li class="font-claude-response-body whitespace-normal break-words pl-2">MS or PhD in EE, CS, or CE with 10+ years of experience in ASIC design verification</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Depth in high-speed I/O verification: protocol-level verification of PCIe or Ethernet, and memory subsystems such as HBM or DDR</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Performance verification methodology: building performance benches and analyzing results, not only functional correctness</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Formal verification and assertion-based methods</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Experience evaluating, integrating, and validating third-party verification IP</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Gate-level simulation and debug</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Emulation and FPGA prototyping platforms</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Post-silicon lab bring-up and functional validation, debugging first-silicon issues to root cause</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Strong understanding of one or more of computation, interconnect, or memory systems</li> <li class="font-claude-response-body whitespace-normal break-words pl-2">Fluency with Claude or other AI tools applied to verification and flow development</li> </ul> <h3> </h3><div class="content-pay-transparency"><div class="pay-input"><div class="description"><p>Base Salary Range:</p></div><div class="title">Base Pay Range</div><div class="pay-range"><span>$180,000</span><span class="divider">—</span><span>$255,000 USD</span></div></div></div><div class="content-conclusion"><p><strong><span style="font-family: helvetica, arial, sans-serif; font-size: 12pt;">Submission Guidelines<br></span></strong><span style="font-family: helvetica, arial, sans-serif; font-size: 12pt;">Please note that in order to be considered an applicant for any position at SambaNova Systems, you must submit an application form for each position for which you believe you are qualified. </span></p> <p><strong><span style="font-family: helvetica, arial, sans-serif; font-size: 12pt;">EEO Policy<br></span></strong><span style="font-family: helvetica, arial, sans-serif; font-size: 12pt;">SambaNova Systems is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard basis of age (40 and over), color, disability, gender identity, genetic information, marital status, military or veteran status, national origin/ancestry, race, religion, creed, sex (including pregnancy, childbirth, breastfeeding), sexual orientation, and any other applicable status protected by federal, state, or local laws.</span></p> <p style="text-align: left;"><span style="font-family: helvetica, arial, sans-serif; font-size: 12pt;"><strong>Benefits Summary for US-Based, Full-Time Employment Positions</strong><br>SambaNova offers a competitive total rewards package, including the base salary, plus equity and benefits. We cover 95% premium coverage for employee medical insurance, and 77% premium coverage for dependents and offer a Health Savings Account (HSA) with employer contribution. We also offer Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans in addition to Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care. Our library of well-being benefits available to you and your dependents includes a full subscription to Headspace, Gympass+ membership with access to physical gyms, One Medical membership, counseling services with an Employee Assistance Program, and much more.</span></p></div>